In the generation-to-generation development of mainframe computer systems, increased speed of operation is sought for a given class of system, and it is therefor useful to minimize the time required to carry out operations which are performed often. This is particularly the case in multiprocessor systems because frequent operations which cause interaction between the processors, or in which one processor briefly takes over a common facility, affects the performance of the entire system.
Some modern computer systems employ multiple processors, each of which has its own private cache memory. As is well known in the art, if a given processor asks its private cache for a block (typically, a group of several operand words) of information which is not currently resident, the private cache control requests the block from one or more additional units in the system, at least one of which should be able to fill the request. The other units may include the private caches of the other processors and a main memory. Other systems, such as that contemplated, interpose a secondary, shared cache between the several private caches and a main memory (and possibly other information sources). In this configuration, a private cache miss in a given processor results in a request to at least the shared cache and, as in the present system, also to all the private caches in a group of processors. If none of these units have a valid copy of the requested block, the shared cache seeks it in main memory or elsewhere.
It is common, in multiprocessor systems in which each processor has its own private cache and in which there is a shared cache, for more than one copy of a given information block to be resident in such private caches and/or the shared cache at a given time. If more than one copy of a given information block is, indeed, resident in the several caches at a given time, it is necessary, to maintain coherence, that only one of the processors "owns" the block and is therefore empowered to modify the block. Therefore, if a processor which has a copy of, but does not own, a block in its private cache wishes to use the block in a fashion which does not require modification, the request sent to its private cache results in a cache hit, and the information is supplied to the processor from its private cache.
However, if a processor which has a copy of, but does not own, the block in its private cache wishes to use the block in a fashion which may require modification, it has no authority to do so. Consequently, it must request ownership of the block If the block is not in use by the current owner and no other processor has an outstanding request to itself assume ownership, ownership is granted (by an arbiter which is the shared cache in the exemplary system) to the requesting processor, and it proceeds with the operation which may result in modification to the block.
But, if the block is either already in use by the current owner or some other processor has already requested ownership, a conflict (interference condition) arises which must be resolved. Typically, this has been achieved by the arbiter notifying the requesting processor that it will not be granted ownership, the processor then waiting to try again or taking up another task and trying again later for ownership of the block of interest. The former approach, which suspends operation of the requesting processor, has an obvious speed penalty. The second approach is better, but the requesting processor must still wait for the arbiter's adverse decision before taking this course of action, and this is another source of adverse effect on performance.
Thus, it will be clear to those skilled in the art of multiprocessing, once these problems are understood, that if the fact that a request for ownership of a block by a given processor cannot be granted can be determined before the request is even broadcast to the other private caches and the shared cache, the requesting processor can more quickly take up other tasks before trying again, and a significant improvement in system speed could be achieved. It is to these ends that the present invention is directed.